The PRACE 7th Project Access Call for Proposals has been opened from February 13 to March 26. In this call the entire PRACE Tier-0 Research Infrastructure is available: CURIE (GENCI@CEA, France) FERMI (CINECA, Italy) HERMIT (GCS@HLRS, Germany) JUQUEEN (GCS@Jülich, Germany) MareNostrum (BSC, Spain) SuperMUC (GCS@LRZ, Germany) Allocations will be for 1 year starting from early [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. This third post is dedicated to the Workshop on Intel Many Integrated Core. Introduction to Workshop on Intel Many Integrated Core by Jim Jeffers (Intel) Intel MIC Architecture – Intel [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. This second post is dedicated to presentations about Multicore Memory Caching Issues by David Henty (EPCC). Multicore Memory Caching Issues – Caches Part 1/2 David Henty (EPCC) – Multicore Memory Caching [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. The three day intensive event focused on programming and tuning techniques for modern multi- and many-core processors with particular focus on the Intel Many Integrated Core (MIC) architecture. Topics included structuring [...]
We would like to make you aware of the following opportunity within the PRACE consortium, with over 1.25 billion CPU Hours of allocatable resource on Tier-0 systems. If you wish to apply for a resource allocation under this scheme then please make sure that you can fulfill the necessary conditions including eligibility and the scalability [...]
