Get “Up to Speed” with Cray Cascade Course CSCS’ next flagship system to be brought into production in April 2013 is a Cray XC30 (Cascade) system with a peak performance of 750 Teraflops using Intel Sandy Bridge processors and with a new network interface chip and an advanced interconnect topology. The CSCS system is currently [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. This third post is dedicated to the Workshop on Intel Many Integrated Core. Introduction to Workshop on Intel Many Integrated Core by Jim Jeffers (Intel) Intel MIC Architecture – Intel [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. This second post is dedicated to presentations about Multicore Memory Caching Issues by David Henty (EPCC). Multicore Memory Caching Issues – Caches Part 1/2 David Henty (EPCC) – Multicore Memory Caching [...]
The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland, hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012. The three day intensive event focused on programming and tuning techniques for modern multi- and many-core processors with particular focus on the Intel Many Integrated Core (MIC) architecture. Topics included structuring [...]
CSCS has the pleasure to announce the following course which will be held at CSCS in Lugano on December 10-12, 2012: Getting the best out of multi-core Modern multi-core x86 processors have 100 times more peak performance than similar single-core processors from ten years ago, but most applications haven’t been able to leverage this power [...]
