Slidecast 3/3 – PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures – Workshop on MIC

The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland,  hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012.

This third post is dedicated to the Workshop on Intel Many Integrated Core.

Introduction to Workshop on Intel Many Integrated Core

by Jim Jeffers (Intel)

Intel MIC Architecture – Intel MIC HW/SW Architecture

by Jim Jeffers (Intel)

Intel MIC Architecture Parallel Programming Tools

by James Reinders (Intel)

Intel MIC Architecture – Getting Started with Intel MIC Coding-Debug

by Michael Klemm (Intel)

Intel MIC Architecture – Memory Usage and Considerations

by Michael Klemm (Intel)

Intel MIC Architecture – Intel MIC User Experiences – Part 1/2

by Tommy Minyard (TACC) and Glenn Brook (NICS)

Intel MIC Architecture – Intel MIC User Experiences – Part 2/2

by Tommy Minyard (TACC) and Glenn Brook (NICS)

Intel MIC Architecture – Intel Math Kernel Library on MIC

by Hans Pabst (Intel)

Intel MIC Architecture – MPI on MIC

by Glenn Brook (NICS) and Hans Pabst (Intel)