Slidecast 1/3 – PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures – Introduction to Vectorization

The Swiss National Supercomputing Centre CSCS in Lugano, Switzerland,  hosted the PRACE Summer School on Code Optimisation for Multi-Core and Intel MIC Architectures on 21-23 June 2012.

The three day intensive event focused on programming and tuning techniques for modern multi- and many-core processors with particular focus on the Intel Many Integrated Core (MIC) architecture.  Topics included structuring code to enable SIMD vectorization, efficient usage of the register, cache and memory hierarchy, use of multi-threading techniques to maximize resource utilization, data locality considerations on multi-socket NUMA nodes, and inter-node communication. Intel specialists introduced the Many Integrated Core architecture and the MIC programming environment, and delved into greater detail of the use of multi- and many-core programming techniques on the Intel MIC. Demonstrations and hands-on sessions integrated throughout the course illustrated the topics in greater depth.

In three posts we publish the slidecasts of the different presentations starting with a brief introduction to vectorization by Neil Stringfellow (CSCS).

Welcome and A Brief Introduction to Vectorization – Part 1/6

A Brief Introduction to Vectorization – Part 2/6

A Brief Introduction to Vectorization – Part 3/6

A Brief Introduction to Vectorization – Part 4/6

A Brief Introduction to Vectorization – Part 5/6

A Brief Introduction to Vectorization – Part 6/6