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DEISA PRACE Symposium 2011

Thursday, March 10th, 2011

The DEISA PRACE Symposium 2011 will be arranged on April 13-14 in Helsinki, Finland, at the National Museum of Finland.

Programme

The symposium is featuring keynote speakers from the US, Asia and Europe as well as scientific speakers from all over Europe, covering major computational science areas in HPC.

The DEISA PRACE Symposium is arranged now for the third time. It is a major European HPC event. The symposium will feature speakers from different scientific communities as well as decision makers in science. The symposium is of major interest to a broad audience: from scientific users, HPC technology experts and vendors, government, EC representatives and industry partners.

The 1st PRACE User Forum is included in the programme of the DEISA PRACE Symposium. The 1st PRACE User Forum will mark the start up of a forum where the PRACE users can discuss their experiences and expectations from the PRACE HPC services and resources.

For more information »

PRACE Summer School in Helsinki

Thursday, March 3rd, 2011

CSC – the Finnish IT Center for Science and SNIC/PDC-Center for High Performance Computing at KTH in Sweden are co-organising a Summer School to be held in Helsinki from 29th August until the 1st September.

The speaker list includes William Gropp (University of Illinois Urbana-Champaign), one of the key authors of MPI (Message Passing Interface) programming paradigm, and Rolf Rabenseifner (HLRS), one of the most renowned researchers of hybrid parallel programming models. The course will include hands-on sessions using the Cray XT4/5 systems at CSC in Finland and the Cray XE6 machine at KTH in Sweden.

The school’s main themes are

  • hybrid MPI and shared-memory programming
  • advanced MPI techniques and hybrid MPI
  • CUDA programming
  • additional lectures in topics such as python in HPC and low-level serial optimisation.

For further details see »

Eligibility – PRACE seasonal schools attendance is free for all academic researchers affiliated to PRACE member countries (N.B. Switzerland is a PRACE member country).

PRACE-1IP kick-off meeting in Garching, Germany

Tuesday, August 31st, 2010

On  30-31 August 2010 the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ) in Garching near Munich hosted the kick-off meeting of the First Implementation Phase Project of PRACE (PRACE-1IP). The Partnership for Advanced Computing in Europe, PRACE (www.prace-project.eu), is a unique persistent pan-European Research Infrastructure for High Performance Computing. PRACE is a project funded in part by the EU´s 7th Framework Programme.

Thomas Eickermann of Jülich Supercomputing Centre welcoming the participants to the kick-off:

Switzerland is being represented in PRACE by CSCS who is contributing to the following working packages:

  • WP2 Evolution of the Research Infrastructure
  • WP3 Dissemination and Training
  • WP8 Support for the procurement and commissioning of HPC services
  • WP9 Future Technologies

(more…)

CSCS evaluated the ease of use of the PGAS programming model for PRACE

Tuesday, March 2nd, 2010

The Partnership for Advanced Computing in Europe’s work package for future petaflop computer technologies beyond 2010 recently assessed 12 prototypes for next-generation computer architectures. The evaluation included full systems, system components, software prototypes, and several research activities.

For example, CSCS evaluated the PGAS programming model using the Cray Compiler Environment for UPC and CAF. CINES and LRZ jointly evaluated a hybrid system containing both thin and fat nodes and compute accelerators within a shared file system. NCF assessed a system of ClearSpeed/PetaPath accelerator boards together with the ClearSpeed programming language. CEA looked at the performance of graphics processing units (GPUs) using CAPS hybrid multicore parallel programming. The CSC studied the maturity of OpenCL and performance improvements for multi-GPU programming on NVIDIA Tesla and AMD Firestream cards. And EPCC evaluated the HARWEST Compiling Environment for developing programs on the FPGA-based Maxwell supercomputer.

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