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Archive for the ‘PRACE’ Category

PRACE-1IP kick-off meeting in Garching, Germany

Tuesday, August 31st, 2010

On  30-31 August 2010 the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ) in Garching near Munich hosted the kick-off meeting of the First Implementation Phase Project of PRACE (PRACE-1IP). The Partnership for Advanced Computing in Europe, PRACE (www.prace-project.eu), is a unique persistent pan-European Research Infrastructure for High Performance Computing. PRACE is a project funded in part by the EU´s 7th Framework Programme.

Thomas Eickermann of Jülich Supercomputing Centre welcoming the participants to the kick-off:

Switzerland is being represented in PRACE by CSCS who is contributing to the following working packages:

  • WP2 Evolution of the Research Infrastructure
  • WP3 Dissemination and Training
  • WP8 Support for the procurement and commissioning of HPC services
  • WP9 Future Technologies

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CSCS evaluated the ease of use of the PGAS programming model for PRACE

Tuesday, March 2nd, 2010

The Partnership for Advanced Computing in Europe’s work package for future petaflop computer technologies beyond 2010 recently assessed 12 prototypes for next-generation computer architectures. The evaluation included full systems, system components, software prototypes, and several research activities.

For example, CSCS evaluated the PGAS programming model using the Cray Compiler Environment for UPC and CAF. CINES and LRZ jointly evaluated a hybrid system containing both thin and fat nodes and compute accelerators within a shared file system. NCF assessed a system of ClearSpeed/PetaPath accelerator boards together with the ClearSpeed programming language. CEA looked at the performance of graphics processing units (GPUs) using CAPS hybrid multicore parallel programming. The CSC studied the maturity of OpenCL and performance improvements for multi-GPU programming on NVIDIA Tesla and AMD Firestream cards. And EPCC evaluated the HARWEST Compiling Environment for developing programs on the FPGA-based Maxwell supercomputer.

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