Attendees of this HP2C training event will learn about the Cray XK6 hybrid multi-core and GPU architecture and its programming environment.
They will learn about the OpenACC directives, which were designed to help users develop and port applications to run on heterogeneous systems. They will have an understanding on how to use the Cray Performance tools to identify “hot areas” in the code to focus the use of OpenACC directives. They will have the opportunity to experiment the OpenACC directives with the Cray Compilation Environment (CCE). In addition, they will learn about the Cray scientific libraries for accelerators and will learn and experiment Allinea’s DDT and Cray’s Performance Tools for debugging and performance tuning of heterogeneous applications on the Cray XK6 systems.
Attendees are encouraged to bring in their own applications and codes for the hands-on sessions. Experts from Cray PE, OpenACC and libsci development and performance tools and Allinea DDT debugger will be present at the meeting for discussions and feedback. We also invite current users who have their applications running successfully on the Cray XK6 system to present brief user experience talks.
Agenda
- Welcome
- Overview of the Cray XK6 system
- Introduction to Cray XK6 Programming Environment
- Support for GPU application development and execution
GPU development environments (CUDA C & Fortran, OpenCL & OpenACC from Cray & PGI)
GPU accelerated libraries
Message passing communication (MPI)
- Introduction to OpenACC
- Development cycle of application porting
Static analysis of the application
Find hot loops
Scoping Analysis
Add OpenMP
Create OpenACC regions from OpenMP regions
- Using libsci_acc
- Debugging
- Performance tuning
The workshop is open for researchers, students and scientific and industrial partners. The intention is to present and discuss the state-of-the-art in high-performance and parallel scientific computing. Presentations will focus on algorithms, applications, and software issues related to high-performance parallel computing. The focus of the workshop on Monday February 6 will be “Scalable Heterogeneous Computing and Programming Models for Computational Science”.
More information and a registration page for the Colloquium or Colloquium+Tutorial are available here »
The fees are:
Colloquium: CHF 50, free for students
Tutorial : CHF 150, CHF 50 for students
The Colloquium Day, February 6, 2012
The following invited speakers will present and discuss the state-of-the-art in high-performance and parallel scientific computing (6 talks of 45 minutes each + poster session):
Prof. Jeff Vetter (Oak Ridge National Laboratory)
Dr. Peter Tang (Intel)
Dr. Brad Chamberlain (Cray)
Prof. Paolo Bientinesi (RWTH Aachen)
Prof. Dimitri Komatitsch (CNRS)
Prof. Bastien Chopard (University of Geneva)
To promote fast exchange of information in our community, a poster session with contributed posters will take place also on Feb 6. Please, encourage your collaborators to register with a poster title and upload an abstract for their posters, the deadline is January 28, 2012.
The Tutorial Day, Feb 7, 2012
On February 7 Speedup will organize a tutorial on Intel Threading Building Blocks taught by Hans Pabst (Intel).
The HPC Advisory Council and the Swiss National Supercomputing Centre will host again the HPC Advisory Council Switzerland Conference 2012 in the
Lugano Convention Centre, Lugano, Switzerland, March 13-15, 2012
The conference will focus on High-Performance Computing education, training (including hands-on) and overview of new developments. The conference will include the following sections per day:
High Speed Networks
High Performance and Parallel I/O
Communication libraries: MPI, SHMEM, PGAS
GPU computing, CUDA, OpenCL
Big Data
Advanced topics / Technologies / development / the road to Exascale
It will bring together system managers, researchers, developers, computational scientists, students and industry affiliates for cross-training and to discuss recent HPC developments and future advancements.
Quantum computers, should they be realized one day, will inevitably make errors. Therefore, they need special error correcting mechanisms. The most important part of it, a so-called Toffoli gate, has now been realized by ETH scientists with superconducting circuits.
Photograph of the superconducting 3-qubit-processor mounted on and connected to a high frequency printed circuit board. (Image: Quantum Device Lab, ETH Zurich)
In a classical computer there happens one error in about ten quadrillion (1016) operations. The goal in quantum computing is to have less than one error in 10.000 (104) operations. Lars Steffen, PhD student in Wallraff´s group and co-author of the publication says that this is a reasonable goal, since errors in quantum computation can never be avoided. «If you want to do complicated quantum information processing, these errors need to be corrected», Andreas Wallraff said.
ETH-professor Andreas Wallraff and his team could now realize a Toffoli gate using a chip with superconducting circuits and could verify its functionality with the newest methods. The results of the study were now published in «Nature».
The Swiss German television SF DRS reported in the transmission Einstein about the research results of Prof. Lucio Mayer of the University of Zurich about the first realistic simulation of the birth of a galaxy similar to our Milky Way.
